Flash memory has become popular recently. A typical flash memory comprises a memory array having a large number of memory cells arranged in blocks. Each of the memory cells is fabricated as a field-effect transistor having a control gate and a floating gate. The floating gate is capable of holding a charge and is separated from source and drain regions contained in a substrate by a layer of thin oxide. Each of the memory cells can be electrically charged by injecting electrons from the drain region through the oxide layer onto the floating gate. The charge can be removed from the floating gate by tunneling the electrons to the source through the oxide layer during an erase operation. Thus the data in a memory cell is determined by the presence or absence of a charge on the floating gate.
Flash cells come in two major types, stack gate flash cells and split gate flash cells, as illustrated in FIGS. 1A and 1B. A stacked gate flash cell has a control gate 14 completely stacked on a floating gate 10. The control gate 14, floating gate 10 and substrate 2 are separated by insulating layers. A split gate flash memory has a control gate 22, which includes a first portion overlaying a floating gate 16 and a second portion directly overlaying the channel. The split gate flash exhibits an improved performance over the stacked gate flash. Specifically, the split gate flash can be constructed to prevent over-erasing that occurs in the stacked gate flash.
Flash memory is operated at high voltages for its read and write operations. The operation power is normally provided by laterally diffused metal-oxide semiconductor (LDMOS) devices that can provide higher power and have higher breakdown voltage than conventional MOS devices. However, the early generation of the LDMOS can only work at voltages up to about 14V. A high voltage LDMOS (HV-LDMOS) was then developed. FIG. 3 illustrates a typical HV-LDMOS. Besides the source 4 and drain 6, which a typical MOS has, the drain has an additional lightly doped drain (LDD) region 31 and the source has an additional sinker region 26. Region 28 is a drift region (also known as a threshold adjust region). Typically, the HV-LDMOS is built in an epitaxy (or implant) region 24, which is formed in substrate 2. The field oxides 38 are formed to increase the breakdown voltage. The reason that the LDMOS shown in FIG. 3 has higher breakdown voltage may be explained as follows. Although it appears that a device is broken down by a voltage applied to it, it is actually the electric field that breaks down the dielectric between the two nodes across which the voltage is applied. When a high voltage is applied between a source/drain and a gate, a strong electric field is generated between the source/drain and the gate. Therefore, by forming thick field oxides (FOX) 38 under the gate 40 and between the source/drain and the gate, where the electrical field is the strongest, the source/drain and the gate are effectively separated far away and the electrical field is lowered, therefore the breakdown voltage is increased.
In the past, flash memory and high voltage peripheral devices were either manufactured in separate chips, or in the same chip but by separate processes. However, it is considerably less expensive and higher performance can be derived from having the flash memory on the same substrate as the higher power and higher voltage devices. Also, it would be desirable to provide an HV-LDMOS while making little or no changes to a current process flow used in forming a flash memory.
A problem with this technique is that it can be quite difficult to simultaneously fabricate the lower power devices with the higher power devices. For instance, the gate dielectric on the lower power devices needs to be quite thin so that the threshold voltage of the device remains low and the switching speed of the device remains quite fast, but in order to be able to handle the higher voltages, the HV-LDMOS needs a thicker gate dielectric. What is needed, therefore, is a method of manufacturing HV-LDMOS devices that is compatible with standard flash memory processes.